View RC32365T365-150BCGI_5031781.PDF datasheet online --- IC-ON-LINE

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1 of 44 october 5, 2005 ? 2005 integrated device technology, inc. dsc 6210 idt and the idt logo are trademarks of integrated device technology, inc. device overview the rc32365 device is a member of the idt? interprise? family of integrated communications processors. this device is designed to address a range of communications applications that require the effi- cient processing of ipsec algorithms. these applications include gate- ways, wireless access points, and virtual private network (vpn) equipment. the key to the rc32365?s efficient processing of ipsec algorithms is a highly progammable se curity engine which off-loads the cpu core of encryption/decryption, hashing, and padding tasks. features list rc32300 32-bit cpu core ? 32-bit mips instruction set ? supports big or little endian operation ? mmu ? 16-entry tlb ? supports variable page sizes and enhanced write algo- rithm ? supports variable number of locked entries ? 8kb instruction cache ? 2-way set associative ? lru replacement algorithm ? 4 word line size ? sub-block ordering ? word parity ? per line cache locking ? 2kb data cache ? 2-way set associative ? lru replacement algorithm ? 4 word line size ? sub-block ordering ? byte parity ? per line cache locking ? can be programmed on a page basis to implement write- through no write allocate, write-through write allocate, or write-back algorithms ? enhanced ejtag and jtag interfaces ? compatible with ieee std. 1149.1-1990 security engine ? dedicated dma channels for high speed data transfers to and from the security engine ? on-chip memory for storage of two security contexts ? supports ecb and cbc modes for the following symmetric encryption algorithms: des, triple des (both two key (k1=k3) and three key (k1!=k3) modes), aes-128 with 128-bit blocks, aes-192 with 128-bit blocks ? hardware support for encryption pad generation and checking using one of seven popular paddi ng algorithms: supports pad algorithm required by ipsec esp ? supports md5 and sha-1 one-way hash functions ? programmable truncation length of computed hash and hmac on a security context basis ? supports concurrent hash and encryption operations block diagram figure 1 rc32365 internal block diagram ejtag mmu d. cache i. cache 32-bit mips cpu core jtag interrupt controller 3 counter timers bus/system dma controller arbiter sdram & device uart (16550) gpio interface pci master/target memory & peripheral bus serial channel gpio pins pci bus controller spi spi bus mii mii integrity monitor ipbus tm interface pci arbiter (host mode) . . security functions security context storage rng encryption unit unit hash 10/100 2 ethernet interfaces controllers including pcmcia support (including pcmcia) rc32365 idt tm interprise tm integrated communications processor
2 of 44 october 5, 2005 rc32365 ? optimized for ipsec ah, esp, and ah+esp (single mac) tunnel and transport mode processing: initialization vector (iv) insertion and extraction, hmac checking, ah mutable field processing for both ipv4 and ipv6 packets, ipsec pad gener- ation and checking random number generator ? true hardware random number generator suitable for security applications: may be used to generate symmetric and public keys, initialization vectors, and nonces ? dedicated dma engine for transferring random numbers to memory ? generates random numbers at a bit rate equal to ipbus clock frequency divided by 32 ? provides 4 word (16 byte) fifo to queue random numbers ? randomness tester continually verifies proper operation of random number generator using a randomness test defined in fips 140-2 pci interface ? 32-bit pci revision 2.2 compliant ? supports host or satellite operation in both master and target modes ? pci clock: supports frequencies from 16 mhz to 66 mhz, pci clock may be asynchronous to master clock (clk) ? pci arbiter in host mode: supports 3 external masters, fixed priority or round robin arbitration ?i 2 o ?like? pci messaging unit two ethernet interfaces ? 10 and 100 mb/s iso/iec 8802-3:1996 compliant ? two ieee 802.3u compatible media independent interfaces (mii) with serial management interface ? mii supports ieee 802.3u auto-negotiation speed selection ? supports 64 entry hash table based multicast address filtering ? 512 byte transmit and receive fifos ? supports flow control functions outlined in ieee std. 802.3x- 1997 sdram controller ? supports up to 512 mb of memory ? 2 chip selects (each supports 2 or 4 banks internal sdram banks) ? 32-bit data width, supports 8/16/32-bit width devices ? supports 16mb, 64mb, 128mb, and 256mb, and 512mb devices ? automatic refresh generation memory and peripheral device controller ? provides ?glueless? interface to standard sram, flash, rom, dual-port memory, and peripheral devices ? provides ?glueless? interface to many 16-bit pcmcia devices ? demultiplexed address and data buses: 32-bit data bus, 26-bit address bus, 6 chip selects, control for external data bus buffers ? supports 8-bit, 16-bit, and 32-bit width devices: automatic byte gathering and scattering ? flexible protocol configurat ion parameters: programmable number of wait states (0 to 63), programmable postread/post- write delay (0 to 31), supports external wait state generation, supports intel and motorola style peripherals ? write protect capability per chip select ? programmable bus transaction timer generates warm reset when counter expires ? supports up to 64mb of memory per chip select dma controller ? 9 dma channels: two channels for each of the two ethernet interfaces (transmit/receive), two channels for pci (pci to memory and memory to pci), two channels for security engine (input/output), one channel for the hardware random number generator ? provides flexible descriptor based operation ? supports unaligned transfers (i.e., source or destination address may be on any byte boundary) with arbitrary byte length general purpose peripherals ? serial port compatible with 16550 universal asynchronous receiver transmitter (uart) ? three general purpose 32-bit counter/timers ? interrupt controller ? serial peripheral interface (spi) supporting host mode ? 16 general purpose i/o (gpio) pins which can be configured as interrupt sources system features ? jtag interface (ieee std. 1149.1 compatible) ? 256 pin cabga package ? 2.5v core supply and 3.3v i/o supply cpu execution core the rc32365 is built around the rc32300 32-bit high performance microprocessor core. the rc32300 implements the enhanced mips-ii isa and helps meet the real-time goals and maximize throughput of communications and consumer systems by providing capabilities such as a prefetch instruction, multiple dsp instructions, and cache locking. the instruction set is largely compatible with the mips32 instruction set, allowing the customer to select from a broad range of software and development tools. cache locking guarantees real-time performance by holding critical code and parameters in the cache for immediate avail- ability. the microprocessor also implements an on-chip mmu with a tlb, making the it fully compliant with the requirements of real time operating systems. security engine the rc32365 incorporates an on-chip security engine that has been designed to accelerate ipsec performance and minimize the amount of performance required by the cpu to process secure packet traffic. the engine includes hardware support for the des, 3des, and aes encryp- tion algorithms and the md5 and sha1 hash functions. the engine also supports hardware-assisted packet processing for the various modes of ipsec, including ah, esp, and ah+esp tunnel and transport modes. two dedicated dma channels are used to transfer data to and from the security engine, allowing the cpu to work on other tasks during this time.
3 of 44 october 5, 2005 rc32365 pci interface the pci interface on the rc32365 is compatible with version 2.2 of the pci specification. an on-chip arbiter supports up to three external bus masters, supporting both fixed prio rity and rotating priority arbitra- tion schemes. the rc32365 can support both satellite and host pci configurations, enabling it to act as a slave controller for a pci add-in card application, or as the primary pci controller in the system. the pci interface can be operated synchronously or asynchronously to the other i/o interfaces on the rc32365 device. pcmcia interface the rc32365 provides a "glueless" connection to a single pcmcia i/o device via the memory and peripheral device controller. the pcmcia interface allows the rc32365 to connect to various types of i/o peripherals including fax modems, storage devices, and wireless lan chipsets. the rc32365 implementation provides a maximum throughput of 160 mbps through the 16-bit wide interface as specified by the pcmcia 2.1 standard. ethernet interface the rc32365 has two ethernet channels supporting 10mbps and 100mbps speeds and provides a st andard media independent interface (mii) off-chip, allowing a wide range of external devices to be connected efficiently. memory and i/o controller the rc32365 incorporates a flexible memory and peripheral device controller providing direct support for sdram, flash rom, sram, pcmcia, and other i/o devices. it can interface directly to 8-bit boot rom for a very low cost system implementation. it also offers various trade-offs in cost / performance for the main memory architecture. the timers implemented on the rc32365 satisfy the requirements of most real time operating systems. dma controller the dma controller off-loads the cpu core from moving data among the on-chip interfaces, external peripherals, and memory. the dma controller supports scatter / gather dma with no alignment restrictions, appropriate for communications and graphics systems. enhanced jtag interface for system debugging, the rc32300 cpu core includes an enhanced jtag (ejtag) interface which operates in run-time mode. thermal considerations the rc32365 is guaranteed in a ambient temperature range of 0 to +70 c for commercial temperature devices and - 40 to +85 for indus- trial temperature devices. revision history march 17, 2003 : initial publication. may 15, 2003 : removed ?write protect capability? from features of the sdram controller. july 9, 2003 : in table 6, changed values for rstn (output). changed values in tables 7, 8, 9, 10, and 17. october 3, 2003 : added 180 mhz speed grade. changed min values in table 7 from 1.8 to 1.2 for all signals except sdclkinp and sdckenp. changed min values for tdo 10b and 10c in table 10 for pciben, etc. and pcigntn/pcireqn from 2.0 to 1.5. february 25, 2004 : deleted reference to rngclk in table 1 (gpio[6]) and table 22. may 25, 2004 : in table 9, signals miixrxclk and miixtxclk, the min and max values for thigh/tlow_9c were changed to 140 and 260 respectively and the min and max values for thigh/tlow_9d were changed to 14.0 and 26.0 respectively. october 5, 2005 : removed 180 mhz speed grade.
4 of 44 october 5, 2005 rc32365 pin description table the following table lists the functions of the pins provided on the rc32365. some of the functions listed may be multiplexed on to the same pin (indicated as alternate functions). to define the active polarity of a signal, a suffix will be us ed. signals ending with an ?n? should be interpreted as being act ive, or asserted, when at a logic zero (low) level. all other signals (including clocks , buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. signal type name/description memory and peripheral bus bdirn o external buffer direction. memory and peripheral bus external data bus buffer direction control. if the rc32365 memory and peripheral bus is connected to the a side of a transceiver such as an idt74fct245, then this pin may be directly connected to the direction control (e.g., bdir) pin of the transceiver. boen[1:0] o external buffer enable. these signals provide output enable control for external buffers on the memory and peripheral data bus. bwen[3:0] o byte write enables. these signals are memory and peripheral bus byte write enable signals. bwen[0] corresponds to byte lane mdata[7:0] bwen[1] corresponds to byte lane mdata[15:8] bwen[2] corresponds to byte lane mdata[23:16] bwen[3] corresponds to byte lane mdata[31:24] csn[5:0] o chip selects. these signals are used to select an external device on the memory and peripheral bus. maddr[21:0] o address bus. 22-bit memory and peripheral bus address bus. maddr[25:22] are available as gpio[5:2] alternate functions. mdata[31:0] i/o data bus. 32-bit memory and peripheral data bus. during a cold reset, bits 0 through 16 of this data bus function as inputs that are used to load the boot configuration vector. oen o output enable. this signal is asserted when data should be driven by an external device on the memory and peripheral bus. rwn o read write. this signal indicates whether the transaction on the memory and peripheral bus is a read transaction or a write transaction. a high level indicates a read from an external device. a low level indicates a write to an external device. waitackn i wait or transfer acknowledge. when configured as wait, this signal is asserted during a mem- ory and peripheral bus transaction to extend the bus cycle. when configured as a transfer acknowledge, this signal is asserted during a transaction to signal the completion of the transac- tion. rasn o sdram row address strobe. row address strobe asserted during memory and peripheral bus sdram transactions. casn o sdram column address strobe. column address strobe asserted during memory and periph- eral bus sdram transactions. sdcsn[1:0] o sdram chip selects. these signals are used to select sdram device(s) on the memory and peripheral bus. sdwen o sdram write enable. this signal is asserted during memory and peripheral bus sdram write transactions. sdclkout o sdram clock output. this clock is used for all sdram memory and peripheral bus operations. sdclkinp i sdram clock input. this clock input is typically a delayed version of sdclkout. data from the sdrams is sampled using this clock. table 1 pin description (part 1 of 6)
5 of 44 october 5, 2005 rc32365 general purpose i/o gpio[0] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0sout alternate function: uart channel 0 serial output. gpio[1] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0sinp alternate function: uart channel 0 serial input. gpio[2] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: maddr[22] alternate function: memory and peripheral bus address bit 22 (output). gpio[3] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: maddr[23] alternate function: memory and peripheral bus address bit 23 (output). gpio[4] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: maddr[24] alternate function: memory and peripheral bus address bit 24 (output). gpio[5] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: maddr[25] alternate function: memory and peripheral bus address bit 25 (output). gpio[6] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. the value of this pin may be used as a counter timer clock input. gpio[7] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: sdckenp alternate function: sdram clock enable output the value of this pin may be used as a counter timer clock input. gpio[8] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: cen1 alternate function: pcmcia chip enable 1 (ce1#) (output). gpio[9] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: cen2 alternate function: pcmcia chip enable 2 (ce2#) (output). gpio[10] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: regn alternate function: pcmcia attribute memory select (reg#) (output). gpio[11] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: iordn alternate function: pcmcia io read (iord#) (output). gpio[12] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: iowrn alternate function: pcmcia io write (iowr#) (output). gpio[13] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcireqn[2] alternate function: pci bus request 2 (output). gpio[14] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcigntn[2] alternate function: pci bus grant 2 (output). signal type name/description table 1 pin description (part 2 of 6)
6 of 44 october 5, 2005 rc32365 gpio[15] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcimuintn alternate function: pci messaging unit interrupt output. serial interface sck i/o serial clock . this signal is used as the serial spi clock output. this pin may be used as a bit input/output port. sdi i/o serial data input . this signal is used to shift in serial spi data. this pin may be used as a bit input/output port. sdo i/o serial data output . this signal is used to shift out serial spi data. this pin may be used as a bit input/output port. pci bus pciad[31:0] i/o pci multiplexed address/data bus . address is driven by a bus master during initial pcifra- men assertion. data is then driven by the bus master during writes or by the bus target during reads. pcicben[3:0] i/o pci multiplexed command/byte enable bus . pci command is driven by the bus master during the initial pciframen assertion. byte enables are driven by the bus master during subsequent data phase(s). pciclk i pci clock . clock used for all pci bus transactions. pcidevseln i/o pci device select . this signal is driven by a bus target to indicate that the target has decoded the address as one of its own address spaces. pciframen i/o pci frame . driven by a bus master. assertion indicates the beginning of a bus transaction. negation indicates the last data. pcigntn[1:0] i/o pci bus grant . in pci host mode with internal arbiter: the assertion of these signals indicates to the agent that the internal rc32365 arbiter has granted the agent access to the pci bus. in pci host mode with external arbiter: pcigntn[0]: asserted by an external arbiter to indicate to the rc32365 that access to the pci bus has been granted. pcigntn[1]: unused and driven high. in pci satellite mode: pcigntn[0]: this signal is asserted by an external arbiter to indicate to the rc32365 that access to the pci bus has been granted. pcigntn[1]: this signal takes on the alternate function of pcieecs and is used as a pci serial eeprom chip select. pciirdyn i/o pci initiator ready . driven by the bus master to indicate that the current data can complete. pcilockn i/o pci lock . this signal is asserted by an external bus master to indicate that an exclusive opera- tion is occurring. pcipar i/o pci parity . even parity of the pciad[31:0] bus. driven by the bus master during address and write data phases. driven by the bus target during the read data phases. pciperrn i/o pci parity error . this signal is asserted by the receiving bus agent 2 clocks after the data is received if a parity error is detected. signal type name/description table 1 pin description (part 3 of 6)
7 of 44 october 5, 2005 rc32365 pcireqn[1:0] i/o pci bus request. in pci host mode with internal arbiter: these signals are inputs whose assertion indicates to the internal rc32365 arbiter that an agent desires ownership of the pci bus. in pci host mode with external arbiter: pcireqn[0]: asserted by the rc32365 to request ownership of the pci bus. pcireqn[1]: unused and driven high. in pci satellite mode: pcireqn[0]: this signal is asserted by the rc32365 to request ownership of the pci bus. pcireqn[1]: function changes to pciidsel and is used as a chip select during configuration read and write transactions. pcirstn i/o pci reset . in host mode, this signal is asserted by the rc32365 to generate a pci reset. in sat- ellite mode, assertion of this signal initiates a warm reset. pciserrn i/o pci system error . this signal is driven by an agent to indicate an address parity error, data par- ity error during a special cycle command, or any other system error. requires an external pull-up. pcistopn i/o pci stop . driven by the bus target to terminate the current bus transaction. for example, to indi- cate a retry. pcitrdyn i/o pci target ready . driven by the bus target to indicate that the current data can complete. ethernet interface mii0cl i ethernet 0 mii collision detected. this signal is asserted by the ethernet phy when a collision is detected. mii0crs i ethernet 0 mii carrier sense. this signal is asserted by the ethernet phy when either the trans- mit or receive medium is not idle. mii0rxclk i ethernet 0 mii receive clock. this clock is a continuous clock that provides a timing reference for the reception of data. mii0rxd[3:0] i ethernet 0 mii receive data. this nibble wide data bus contains the data received by the ether- net phy. mii0rxdv i ethernet 0 mii receive data valid. the assertion of this signal indicates that valid receive data is in the mii receive data bus. mii0rxer i ethernet 0 mii receive error. the assertion of this signal indicates that an error was detected somewhere in the ethernet frame currently being sent in the mii receive data bus. mii0txclk i ethernet 0 mii transmit clock. this clock is a continuous clock that provides a timing reference for the transfer of transmit data. mii0txd[3:0] o ethernet 0 mii transmit data. this nibble wide data bus contains the data to be transmitted. mii0txenp o ethernet 0 mii transmit enable. the assertion of this signal indicates that data is present on the mii for transmission. mii0txer o ethernet 0 mii transmit coding error. when this signal is asserted together with miitxenp, the ethernet phy will transmit symbols which are not valid data or delimiters. mii1cl i ethernet 1 mii collision detected. this signal is asserted by the ethernet phy when a collision is detected. mii1crs i ethernet 1 mii carrier sense. this signal is asserted by the ethernet phy when either the trans- mit or receive medium is not idle. mii1rxclk i ethernet 1 mii receive clock. this clock is a continuous clock that provides a timing reference for the reception of data. signal type name/description table 1 pin description (part 4 of 6)
8 of 44 october 5, 2005 rc32365 mii1rxd[3:0] i ethernet 1 mii receive data. this nibble wide data bus contains the data received by the ether- net phy. mii1rxdv i ethernet 1 mii receive data valid. the assertion of this signal indicates that valid receive data is in the mii receive data bus. mii1rxer i ethernet 1 mii receive error. the assertion of this signal indicates that an error was detected somewhere in the ethernet frame currently being sent in the mii receive data bus. mii1txclk i ethernet 1 mii transmit clock. this clock is a continuous clock that provides a timing reference for the transfer of transmit data. mii1txd[3:0] o ethernet 1 mii transmit data. this nibble wide data bus contains the data to be transmitted. mii1txenp o ethernet 1 mii transmit enable. the assertion of this signal indicates that data is present on the mii for transmission. mii1txer o ethernet 1 mii transmit coding error. when this signal is asserted together with miitxenp, the ethernet phy will transmit symbols which are not valid data or delimiters. miimdc o mii management data clock. this signal is used as a timing reference for transmission of data on the management interface. miimdio i/o mii management data. this bidirectional signal is used to transfer data between the station man- agement entity and the ethernet phy. ejtag / jtag jtag_tms i jtag mode . the value on this signal controls the test mode select of the boundary scan logic or jtag controller. when using the ejtag debug interface, this pin should be left disconnected (since there is an internal pull-up) or driven high. ejtag_tms i ejtag mode . the value on this signal controls the test mode select of the ejtag controller. when using the jtag boundary scan, this pin should be left disconnected (since there is an inter- nal pull-up) or driven high. jtag_trst_n i jtag reset . this active low signal asynchronously resets the boundary scan logic, jtag tap controller, and the ejtag debug tap controller. an external pull-up on the board is recom- mended to meet the jtag specification in cases where the tester can access this signal. how- ever, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board 3) clock jtag_tck while holding ejtag_tms and/or jtag_tms high. jtag_tck i jtag clock . this is an input test clock used to clock the shifting of data into or out of the bound- ary scan logic, jtag controller, or the ejtag controller. jtag_tck is independent of the sys- tem and the processor clock with a nominal 50% duty cycle. jtag_tdo o jtag data output . this is the serial data shifted out from the boundary scan logic, jtag con- troller, or the ejtag controller. when no data is being shifted out, this signal is tri-stated. jtag_tdi i jtag data input . this is the serial data input to the boundary scan logic, jtag controller, or the ejtag controller. signal type name/description table 1 pin description (part 5 of 6)
9 of 44 october 5, 2005 rc32365 pin characteristics miscellaneous clk i master clock. this is the master clock input. the processor frequency is a multiple of this clock frequency. this clock is used as the system clock for all memory and peripheral bus operations except those associated with sdrams. coldrstn i cold reset. the assertion of this signal initiates a cold reset. this causes the processor state to be initialized, boot configuration to be loaded, and the internal pll to lock onto the master clock (clk). rstn i/o reset. the assertion of this bidirectional signal initiates a warm reset. this signal is asserted by the rc32365 during a warm reset. it can also be asserted by an external device to force the rc32365 to take a warm reset exception. pin name type buffer i/o type internal resistor external resistor 1 memory and peripheral bus bdirn o lvttl high drive boen[1:0] o lvttl high drive bwen[3:0] o lvttl high drive csn[5:0] o lvttl high drive maddr[21:0] o lvttl high drive mdata[31:0] i/o lvttl high drive oen o lvttl high drive rwn o lvttl high drive waitackn i lvttl sti 2 pull-up rasn o lvttl high drive casn o lvttl high drive sdcsn[1:0] o lvttl high drive sdwen o lvttl high drive sdclkout o lvttl high drive sdclkinp i lvttl sti pull-up general purpose i/o gpio[15:13] i/o pci pci gpio[12:0] i/o lvttl low drive pull-up serial interface sck i/o lvttl low drive pull-up pull-up on board sdi i/o lvttl low drive pull-up pull-up on board sdo i/o lvttl low drive pull-up pull-up on board pci bus interface pciad[31:0] i/o pci pci pcicben[3:0] i/o pci pci pciclk i pci pci pcidevseln i/o pci pci pull-up on board table 2 pin characteristics (part 1 of 2) signal type name/description table 1 pin description (part 6 of 6)
10 of 44 october 5, 2005 rc32365 pciframen i/o pci pci pull-up on board pcigntn[1:0] i/o pci pci pull-up on board pciirdyn i/o pci pci pull-up on board pcilockn i/o pci pci pcipar i/o pci pci pciperrn i/o pci pci pcireqn[1:0] i/o pci pci pull-up on board pcirstn i/o pci pci pull-down on board pciserrn i/o pci open collector; pci pull-up on board pcistopn i/o pci pci pull-up on board pcitrdyn i/o pci pci pull-up on board ethernet interfaces mii0cl i lvttl sti pull-up mii0crs i lvttl sti pull-up mii0rxclk i lvttl sti pull-up mii0rxd[3:0] i lvttl sti pull-up mii0rxdv i lvttl sti pull-up mii0rxer i lvttl sti pull-up mii0txclk i lvttl sti pull-up mii0txd[3:0] o lvttl low drive mii0txenp o lvttl low drive mii0txer o lvttl low drive mii1cl i lvttl sti pull-up mii1crs i lvttl sti pull-up mii1rxclk i lvttl sti pull-up mii1rxd[3:0] i lvttl sti pull-up mii1rxdv i lvttl sti pull-up mii1rxer i lvttl sti pull-up mii1txclk i lvttl sti pull-up mii1txd[3:0] o lvttl low drive mii1txenp o lvttl low drive mii1txer o lvttl low drive miimdc o lvttl low drive miimdio i/o lvttl low drive pull-up ejtag / jtag jtag_tms i lvttl sti pull-up see chapters 22 and 23 of the rc32365 user reference manual ejtag_tms i lvttl sti pull-up jtag_trst_n i lvttl sti pull-up jtag_tck i lvttl sti pull-up jtag_tdo o lvttl low drive jtag_tdi i lvttl sti pull-up miscellaneous clk i lvttl sti coldrstn i lvttl sti rstn i/o lvttl low drive / sti pull-up pull-up on board 1. external pull-up required in most system applications. some applications may require additional pull-ups not identified in this table. 2. schmidt trigger input (sti). pin name type buffer i/o type internal resistor external resistor 1 table 2 pin characteristics (part 2 of 2)
11 of 44 october 5, 2005 rc32365 boot configuration vector the boot configuration vector is read into the rc32365 during cold reset. the vector defines parameters in the rc32365 that are essential to oper- ation when cold reset is complete. the encoding of boot configuration vector is described in table 3, and the vector input is illustrated in figure 4. signal name/description mdata[2:0] cpu clock multiplier . this field specifies the value by which the pll multiplies the master clock input (clk) to obtain the processor clock frequency (pclk). 0x0 - multiply by 2 0x1 - 0x7 ? reserved mdata[3] endian. this bit specifies the endianness. 0x0 - little endian 0x1 - big endian mdata[4] reserved. this pin may be driven high or low during boot configuration and its state is recorded in the boot configuration vector (bcv) field of the bcv register. this reserved bit may be used to pass boot configuration parameters to software. mdata[6:5] boot device width . this field specifies the width of the boot device (i.e., device 0). 0x0 - 8-bit boot device width 0x1 - 16-bit boot device width 0x2 - 32-bit boot device width 0x3 - reserved mdata[7] reset mode . this bit specifies the length of time the rstn signal is driven. 0x0 - normal reset: rstn driven for minimum of 4096 clock cycles 0x1 - reserved mdata[8] disable watchdog timer . when this bit is set, the watchdog timer is disabled following a cold reset. 0x0 - watchdog timer is enabled 0x1 - watchdog timer is disabled mdata[11:9] pci mode . this bit controls the operating mode of the pci bus interface. the initial value of the en bit in the pcic register is determined by the pci mode. 0x0 - disabled (en initial value is zero) 0x1 - pci satellite mode with pci target not ready (en initial value is one) 0x2 - pci satellite mode with suspended cpu execution (en initial value is one) 0x3 - pci host mode with external arbiter (en initial value is zero) 0x4 - pci host mode with internal arbiter using fixed priority arbitration algorithm (en initial value is zero) 0x5 - pci host mode with internal arbiter using round robin arbitration algorithm (en initial value is zero) 0x6 - reserved 0x7 - reserved mdata[15:12] reserved . these pins may be driven high or low during boot configuration and their state is recorded in the boot configuration vector (bcv) field of the bcv register. these reserved bits may be used to pass boot configuration parameters to software. table 3 boot configuration vector encoding
12 of 44 october 5, 2005 rc32365 logic diagram the following logic diagram shows the primary pin functions of the rc32365. figure 1 rc32365 logic diagram miscellaneous signals memory and peripheral bus clk coldrstn rstn 4 miimdc miimdio mii0cl mii0crs mii0rxclk mii0rxd[3:0] mii0rxdv mii0rxer mii0txclk mii0txd[3:0] mii0txenp mii0txer mii1cl mii1crs mii1rxclk mii1rxd[3:0] mii1rxdv mii1rxer mii1txclk mii1txd[3:0] mii1txenp mii1txer bdirn boen[1:0] bwen[3:0] csn[5:0] maddr[21:0] mdata[31:0] oen rwn waitackn gpio[15:0] sdo jtag_trst_n jtag_tck jtag_tdo jtag_tdi ejtag_tms 4 4 4 16 32 22 6 4 ejtag / jtag signals general purpose i/o serial i/o ethernet rc32365 vcccore vcci/o vss vccpll vsspll power/ground sdi sck jtag_tms rasn casn sdclkinp sdcsn[1:0] 2 sdwen 2 sdclkout pciad[31:0] pcicben[3:0] pciclk pcidevseln pciframen pcigntn[1:0] pciirdyn pcilockn pcipar pciperrn pcireqn[1:0] pcirstn pciserrn pcistopn pcitrdyn 2 2 4 32 pci bus
13 of 44 october 5, 2005 rc32365 ac timing definitions below are examples of the ac timing c haracteristics used throughout this document. figure 2 ac timing definitions waveform symbol definition tper clock period. tlow clock low. amount of time the clock is low in one clock period. thigh clock high. amount of time the clock is high in one clock period. trise rise time. low to high transition time. tfall fall time. high to low transition time. tjitter jitter. amount of time the reference clock (or signal) edge can vary on either the rising or falling edges. tdo data out. amount of time after the reference clock edge that the output will become valid. the minimum time represents the d ata output hold. the maximum time represents the earliest time the designer can use the data. tzd z state to data valid. amount of time after the reference clock edge that the tri-stated output takes to become valid. tdz data valid to z state. amount of time after the reference clock edge that the valid output takes to become tri-stated. tsu input set-up. amount of time before the reference clock edge that the input must be valid. thld input hold. amount of time after the reference clock edge that the input must remain valid. tpw pulse width. amount of time the input or output is active for asynchronous signals. tslew slew rate. the rise or fall rate for a signal to go from a high to low, or low to high. x(clock) timing value. this notation represents a value of ?x? multiplied by the clock time period of the specified clock. using 5(clk) as an example: x = 5 and the oscillator clock (clk) = 25mhz, then the timing value is 200. tskew skew. the amount of time two signal edges deviate from one another. table 4 ac timing definitions tdz tzd tdo tpw tpw thld tsu tlow thigh thigh tper clock output signal 1 output signal 2 input signal 1 signal 1 tjitter trise tfall tdo signal 2 signal 3 tskew
14 of 44 october 5, 2005 rc32365 clock parameters the values given below are based on systems running at recomm ended supply voltages and operating temperatures, as shown in tabl es 14 and 15. figure 3 clock parameters waveform parameter symbol reference edge 150mhz units timing diagram reference min max pclk 1 1. the cpu pipeline clock (pclk) speed is selected during cold reset by the boot configuration vector (see table 3). frequency none 100 150 mhz see figure 3 clk 2,3 2. ethernet clock (miixrxclk and miixtxclk) frequency must be less than or equal to 1/2 clk frequency. 3. pci clock (pciclk) frequency must be less than or equal to two times clk. frequency none 50 75 mhz tper_5a 13.3 20 ns thigh_5a, tlow_5a 40 60 % of tper_5a trise_5a, tfall_5a ?3.0 ns tjitter_5a ? 250 ps table 5 rc32365 clock parameters tlow_5a thigh_5a tper_5a clk trise_5a tfall_5a tjitter_5a tjitter_5a
15 of 44 october 5, 2005 rc32365 ac timing characteristics the values given below are based on systems running at recommended operating supply voltages and temperatures as shown in table s 14 and 15. signal symbol reference edge 150mhz unit conditions timing diagram reference min max reset and system coldrstn tpw_6a 1 1. the values for this symbol were determined by calculation, not by testing. none 110 ? ms cold reset see figures 4 and 5 trise_6a ? 5.0 ns cold reset rstn 2 (output) 2. rstn is a bidirectional signal. it is treated as an asynchronous input. tdo_6b clk rising 2.0 9.0 ns cold reset rstn 2 (input) tpw_6c 1 none 2(clk) ? ns cold reset mdata[15:0] boot configuration vector thld_6d coldrstn rising 3.0 ? ns cold reset tdz_6d 1 coldrstn falling ? 2(clk) ns cold reset tdz_6d 1 rstn falling ? 2(clk) ns warm reset tzd_6d 1 rstn rising 3.0 ? ns warm reset table 6 reset and system ac timing characteristics
16 of 44 october 5, 2005 rc32365 figure 4 cold reset ac timing waveform figure 5 warm reset ac timing waveform boot vector sdclkout coldrstn rstn mdata[31:0] bdirn boen[1:0] >= 100 ms >=10ms >= 4096 clk clock cycles >= 4096 clk clock cycles tpw_6a tdo_6b clk 1 ffff_ffff thld_6d 1. coldrstn asserted by external logic. 2. rc32365 asserts rstn, asserts boen[0] low, drives bdirn low, and tri-states the data bus in response. 3. external logic begins driving valid boot configuration vector on the data bus, and the rc32365 starts sampling it. 4. external logic negates coldrstn and tri-states the boot configuration vector on mdata[15:0]. the boot configuration vector mu st not be tri-stated before coldrstn is deas- serted. the rc32365 stops sampling the boot configuration vector. 5. the rc32365 starts driving the data bus, mdata[31:0], deasserts boen[0] high, and drives bdirn high. 6. sysclk may be held constant after this point if hold sysclk constant is selected in the boot configuration vector. 7. rstn negated by the rc32365. 8. cpu begins executing by taking mips reset exception, and the rc32365 starts sampling rstn as a warm reset input. 2 34 56 7 8 trise_6a tdz_6d (rstn ignored during this period to allow pull-up to drive signal high) (rstn sampled) active deasserted active clk coldrstn rstn mdata[31:0] mem control signals >= 4096 clk clock cycles >= 4096 clk clock cycles (rstn ignored during this period to allow pull-up to drive signal high) 1. warm reset condition caused by either rstn asserted, write to reset register, or bus transaction timer time-out. the rc32365 asserts rstn output low in response. 2. the rc32365 tri-states the data bus, mdata[31:0], and deasserts all memory control signals, such as rasn, casn, rwn, oen, etc . 3. the rc32365 deasserts rstn. 4. the rc32365 starts driving the data bus, mdata[31:0], again, but does not sample the rstn input. 5. cpu begins executing by taking a mips soft reset exception and also starts sampling the rstn input again. ffff_ffff 12 34 5 tzd_6d tdz_6d (rstn sampled)
17 of 44 october 5, 2005 rc32365 signal symbol reference edge 150mhz unit conditions timing diagram reference min max memory and peripheral bus - sdram access mdata[31:0] tsu_7a sdclkinp rising 1.0 ? ns see figures 6 and 7 thld_7a 1.7 ? ns tdo_7a sdclkout rising 1.2 6.0 ns tdz_7a 1 1. the values for this symbol were determined by calculation, not by testing. 1.2 7.0 ns tzd_7a 1 1.2 8.0 ns maddr[20:2] tdo_7b sdclkout rising 1.2 6.0 ns rasn tdo_7c sdclkout rising 1.2 6.0 ns casn tdo_7d sdclkout rising 1.2 6.0 ns sdwen tdo_7e sdclkout rising 1.2 6.0 ns sdcsn[1:0] tdo_7f sdclkout rising 1.2 6.0 ns bdirn tdo_7g sdclkout rising 1.2 6.0 ns boen[1:0] tdo_7h sdclkout rising 1.2 6.0 ns bwen[3:0] tdo_7i sdclkout rising 1.2 6.0 ns sdclkinp tdelay_7k sdclkout rising 0.0 2.5 ns see figures 6 and 8 sdckenp tdo_7l sdclkout rising 2.0 6.0 ns table 7 memory and peripheral bus ac timing characteristics
18 of 44 october 5, 2005 rc32365 figure 6 memory and peripheral bus ac timing waveform - sdram read access addr 1111 be's 1111 nop read nop 11 chip-sel 11 11 buffer enables 11 data tzd_7a tdz_7a tdo_7h tdo_7h tdo_7g tdo_7g tdo_7f tdo_7c, 7d, and 7e tdo_7i tdo_7b thld_7a tsu_7a clk sdclkout maddr[21:0] bwen[3:0] cmd[2:0]* sdcsn[1:0] bdirn boen[1:0] mdata[31:0] sdclkinp sdram cas latency tdelay_7k * note: cmd[2:0] = {rasn, casn, sdwen} rc32365 samples read data
19 of 44 october 5, 2005 rc32365 figure 7 memory and peripheral bus ac timing waveform - sdram write access addr 1111 be's 1111 nop write nop 11 chip-sel 11 11 buff enable 11 data tdo_7a tdo_7h tdo_7g tdo_7f tdo_7c, 7d, and 7e tdo_7i tdo_7b clk sdclkout maddr[21:0] bwen[3:0] cmd[2:0]* sdcsn[1:0] bdirn boen[1:0] mdata[31:0] * note: cmd[2:0] = {rasn, casn, sdwen} sdram samples write data
20 of 44 october 5, 2005 rc32365 figure 8 sdclkout - sdclkinp relationship signal symbol reference edge 150mhz unit conditions timing diagram reference min max memory and peripheral bus 1 ? device access mdata[31:0] tsu_8a clk rising 2.5 ? ns see figures 9 and 10 thld_8a 1.0 ? ns tdo_8a 2.0 6.5 ns tdz_8a 2 2.0 9.5 ns tzd_8a 2 2.0 10.5 ns maddr[21:0] tdo_8b clk rising 2.0 6.5 ns maddr[25:22] tdo_8c clk rising 3.0 7.5 ns csn[5:0] tdo_8d clk rising 2.0 6.5 ns rwn tdo_8e clk rising 2.0 6.5 ns oen tdo_8f clk rising 2.0 6.5 ns bwen[1:0] tdo_8g clk rising 2.0 6.5 ns bdirn tdo_8h clk rising 2.0 6.5 ns boen[1:0] tdo_8i clk rising 2.0 6.5 ns waitackn 3 tsu_8j clk rising 2.0 ? ns thld_8j 0.5 ? ns tpw_8j 2 none 2(clk) ?ns table 8 memory and peripheral bus ac timing characteristics ? device access (part 1 of 2) rc32365 sdram sram, eprom, etc. external sdclkout sdclkinp clk memory bus tdelay_7k rstn coldrstn vcc pull-up buffer
21 of 44 october 5, 2005 rc32365 figure 9 memory and peripheral bus ac timing waveform - device read access cen1 4 , cen2 4 tdo_8k clk rising 3.0 7.5 ns see figures 9 and 10 (cont.) regn 4 tdo_8l clk rising 3.0 7.5 ns iordn 4 tdo_8m clk rising 3.0 7.5 ns iowrn 4 tdo_8n clk rising 3.0 7.5 ns 1. the rc32365 provides bus turnaround cycles to prevent bus contention when going from a read to write and write to read. for exa mple, there are no cycles where an external device and the rc32365 are both driving. see chapter 6, device controller, in the rc32365 user reference manual. 2. the values for this symbol were determined by calculation, not by testing. 3. waitackn must meet the setup and hold times if it is synchronous or the minimum pulse width if it is asynchronous. 4. cen1, cen2, regn, iordn, and iowrn are alternate functions of gpio[12:8]. signal symbol reference edge 150mhz unit conditions timing diagram reference min max table 8 memory and peripheral bus ac timing characteristics ? device access (part 2 of 2) addr[21:0] addr[25:22] 1111 data tdo_8i tdo_8i tdo_8h tdo_8h tzd_8a tdz_8a tdo_8f tdo_8f tdo_8d tdo_8d tdo_8c tdo_8b thld_8a tsu_8a clk maddr[21:0] maddr[25:22] rwn csn[5:0] bwen[3:0] oen mdata[31:0] bdirn boen[1:0] waitackn rc32365 samples read data
22 of 44 october 5, 2005 rc32365 figure 10 memory ac and peripheral bus timing waveform - device write access addr[21:0] addr[25:22] 1111 byte enables 1111 data tdo_8i tdo_8a tdo_8g tdo_8d tdo_8e tdo_8c tdo_8b clk maddr[21:0] maddr[25:22] rwn csn[5:0] bwen[3:0] oen mdata[31:0] bdirn boen[1:0] waitackn
23 of 44 october 5, 2005 rc32365 signal symbol reference edge 150mhz unit conditions timing diagram reference min max ethernet 1 1. there are two mii interfaces and the timing is the same for each. ?x? represents interface 0 or 1 (for example, miixrxclk can b e either mii0rxclk or mii1rxclk). miimdc tper_9a none 53.3 ? ns see figure 11 thigh_9a, tlow_9a 23.0 ? ns miimdio tsu_9b miimdc rising 10.0 ? ns thld_9b 1.0 ? ns tdo_9b 1(iclk) 3(iclk) ns miixrxclk, miixtx- clk 2 2. the ethernet clock (miixrxclk and miixtxclk) frequency must be equal to or less than 1/2 clk (miixrxclk and miixtxclk <= 1/2(clk)). tper_9c none 399.96 400.4 ns 10 mbps thigh_9c, tlow_9c 140 260 ns trise_9c, tfall_9c ?3.0 ns miixrxclk, miixtxclk 2 tper_9d none 39.9 40.0 ns 100 mbps thigh_9d, tlow_9d 14.0 26.0 ns trise_9d, tfall_9d ?2.0 ns miixrxd[3:0], miixrxdv, miixrxer tsu_9e miixrxclk rising 3.0 ? ns thld_9e 2.0 ? ns miixtxd[3:0], miixtxenp, miixtxer tdo_9f miixtxclk rising 5.0 13 ns table 9 ethernet ac timing characteristics
24 of 44 october 5, 2005 rc32365 figure 11 ethernet ac timing waveform signal symbol reference edge 150mhz unit conditions timing diagram reference min max pci 1 pciclk 2 tper_10a none 15.0 30.0 ns 66 mhz pci see figure 12 thigh_10a, tlow_10a 6.0 ? ns tslew_10a 1.5 4.0 v/ns table 10 pci ac timing characteristics (part 1 of 2) tdo_9b tdo_9b tdo_9f tdo_9f thld_9b tsu_9b tlow tlow_9a thigh_9a tper_9a tlow_9d tlow thigh_9d tper_9d thld_9e tsu_9e tlow_9d tlow thigh_9d tper_9d miixrxclk miixrxdv, miixrxd[3:0], miixrxer miixtxclk miixtxen, miixtxd[3:0], miixtxer miixmdc miixmdio (output) miixmdio (input)
25 of 44 october 5, 2005 rc32365 pciad[31:0], tsu_10b pciclk rising 3.0 ? ns thld_10b 0 ? ns tdo_10b 2.0 6.0 ns tdz_10b 3 ? 14.0 ns tzd_10b 3 2.0 ? ns pciben[3:0], pcidevseln, pciframen,pciir- dyn, pcilockn, pci- par, pciperrn, pcistopn, pcitrdy 4 tsu_10b 5 pciclk rising 5.0 ? ns thld_10b 0 ? ns tdo_10b 1.5 6.0 ns pcigntn[2:0], pcireqn[2:0] 4,6 tsu_10c pciclk rising 5.0 ? ns thld_10c 0 ? ns tdo_10c 1.5 6.0 ns pcirstn (output) 7 tpw_10d 3 none 4000 (clk) ? ns see figure 13 pcirstn (input) 7,8 tpw_10e 3 none 2(clk) ? ns see figure 14 tdz_10e 3 pcirstn falling 6(clk) ? ns pciserrn 9 tsu_10f pciclk rising 3.0 ? ns see figure 12 thld_10f 0 ? ns tzd_10f 3 2.0 6.0 ns pcimuintn 10 tzd_10g 3 pciclk rising 4.7 11.1 ns 1. this pci interface conforms to the pci local bus specification, rev 2.2 at 33mhz. 2. pciclk must be equal to or less than two times clk (pciclk <= 2(clk)). 3. the values for this symbol were determined by calculation, not by testing. 4. pci local bus specification, rev 2.2 specifies tval minimum = 2.0ns. 5. the 5ns minimum set-up time conforms to the pci local bus specification, rev 2.2 at 33mhz. at 66mhz, the 5ns minimum set-up time provides a wide margin of 4ns, which is sufficient to ensure a working design at such frequency. 6. pcigntn[2] and pcireqn[2] are alternate functions of gpio[14] and gpio[13] respectively. 7. pcirstn is an output in host mode and an input in satellite mode. 8. to meet the pci delay specification from reset asserted to outputs floating, the pci reset should be logically combined with th e cold- rstn input, instead of input on pcirstn. 9. pciserrn uses open collector i/o types. 10. pcimuintn is an alternate function of gpio[15]. signal symbol reference edge 150mhz unit conditions timing diagram reference min max table 10 pci ac timing characteristics (part 2 of 2)
26 of 44 october 5, 2005 rc32365 figure 12 pci ac timing waveform figure 13 pci ac timing waveform ? pci reset in host mode tdo_10c tzd_10b tdz_10b tdo_10b thld_10c tsu_10c thld_10b tsu_10b thigh_10a tper_10a tper_10a valid valid pciclk bussed output point to point output bussed input point to point input tlow_10a tpw_10d tpw_10d pci interface enabled cold reset warm reset coldrstn pcirstn (output) rstn note: during and after cold reset, pcirstn is tri-stated and requires a pull-down to reach a low state. after the pci interface is enabled in host mode, pcirstn will be driven either high or low depending on the (tri-state) reset state of the rc32365.
27 of 44 october 5, 2005 rc32365 figure 14 pci ac timing waveform ? pci reset in satellite mode signal symbol reference edge 150mhz unit conditions timing diagram reference min max spi 1 1. in spi mode, the sck period and sampling edge are programmable. in pci mode, the sck period is fixed and the sampling edge is rising. sck tper_12a none ? 1920 ns 33 mhz pci see figures 15 through 18 tper_12a ? 960 ns 66 mhz pci tper_12a 100 166667 ns spi thigh_12a, tlow_12a 930 990 ns 33 mhz pci thigh_12a, tlow_12a 465 495 ns 66 mhz pci thigh_12a, tlow_12a 40 83353 ns spi sdi tsu_12b sck rising or falling 60 ? ns spi or pci thld_12b 60 ? ns sdo tdo_12c sck rising or falling 0 60 ns spi or pci pcieecs 2 2. pcieecs is the pci serial eeprom chip select. it is an alternate function of pcigntn[1]. tdo_12d sck rising or falling 060 ns pci sck, sdi, sdo 3 3. in bit i/o mode, sck, sdi, and sdo must meet the setup and hold times if they are synchronous or the minimum pulse width if the y are asynchronous. tpw_12e none 2(clk) ?ns table 11 spi ac timing characteristics tdz_10e tpw_10e tpw_10e warm reset clk pcirstn (input) rstn mdata[15:0] pci bus signals
28 of 44 october 5, 2005 rc32365 figure 15 spi ac timing waveform ? pci configurations load figure 16 spi ac timing waveform ? clock polarity 0, clock phase 0 tdo_12c tdo_12d thld_12b tsu_12b tlow_12a tlow_12a thigh_12a thigh_12a tper_12a msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb loading pci configuration registers through spi from an eeprom. msb bit 6 bit 4 bit 2 lsb bit 5 bit 3 bit 1 sck pcieecs sdi sdo tdo_12c thld_12b tsu_12b tlow_12a thigh_12a tper_12a msb bit 6 bit 4 bit 5 bit 3 bit 2 bit 1 lsb control bits cpol = 0, cpha = 0 in the spi control register, spc. msb bit 6 bit 4 bit 2 lsb bit 5 bit 3 bit 1 sck sdi sdo
29 of 44 october 5, 2005 rc32365 figure 17 spi ac timing waveform ? clock polarity 0, clock phase 1 figure 18 spi ac timing waveform ? bit i/o mode tdo_12c thld_12b tsu_12b tlow_12a thigh_12a tper_12a msb bit 6 bit 4 bit 5 bit 3 bit 2 bit 1 lsb control bits cpol = 0, cpha = 1 in the spi control register, spc. msb bit 6 bit 4 bit 5 bit 3 bit 1 bit 2 lsb sck sdi sdo tdo_12e tdo_12e tpw_12e tpw_12e thld_12e tsu_12e clk sck, sdi, sdo (output) sck, sdi, sdo (input) sck, sdi, sdo (asynchronous input)
30 of 44 october 5, 2005 rc32365 figure 19 gpio ac timing waveform signal symbol reference edge 150mhz unit conditions timing diagram reference min max gpio gpio[15:0] 1 1. gpio signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. tsu_13a clk rising 4.0 ? ns see figure 19 thld_13a 2.0 ? ns tdo_13a 2.0 14.0 ns tpw_13b 2 2. the values for this symbol were determined by calculation, not by testing. none 2(clk) ?ns table 12 gpio ac timing characteristics tdo_13a tdo_13a tpw_13b tpw_13b thld_13a tsu_13a clk gpio (synchronous output) gpio (synchronous input) gpio (asynchronous input)
31 of 44 october 5, 2005 rc32365 figure 20 ejtag/jtag ac timing waveform signal symbol reference edge 150mhz unit conditions timing diagram reference min max ejtag and jtag jtag_tck tper_14a none 100 ? ns see figure 20 thigh_14a, tlow_14a 40 ? ns trise_14a, tfall_14a ?5.0 ns jtag_tdi tsu_14b jtag_tck rising 4.0 ? ns thld_14b 4.0 ? ns jtag_tms tsu_14c 4.0 ? ns thld_14c 4.0 ? ns ejtag_tms tsu_14d 4.0 ? ns thld_14d 4.0 ? ns jtag_tdo tdo_14e jtag_tck falling ? 12.5 ns tdz_14e 1 ? 15.0 ns jtag_trst_n tpw_14f 1 1. the values for this symbol were determined by calculation, not by testing. none 100 ? ns vsense trise_16f none ? 2 sec measured from 0.5v (t active ) see figure 22 table 13 ejtag/jtag ac timing characteristics tpw_14f tpw_1 tdz_14e tdo_14e thld_14d tsu_14d thld_14c tsu_14c thld_14b tsu_14b tlow_14a tlow_1 tper_14a thigh_14a jtag_tck jtag_tdi jtag_tms ejtag_tms jtag_tdo jtag_trst_n
32 of 44 october 5, 2005 rc32365 the ieee 1149.1 specification requires that the jtag and ejtag tap controllers be reset at power-up whether or not the interfac es are used for a boundary scan or a probe. reset can occur through a pull-down resi stor on jtag_trst_n if the probe is not connected. however, on-chip pull-up resistors are implemented on the rc32365 due to an ieee 1149.1 requirement. having on-chip pull- up and external pull-down resis tors for the jtag_trst_n signal requires special care in the design to ensure t hat a valid logical level is provided to jtag_trst_n, such as using a small external pull-down resistor to ensure this level overrides the on- chip pull-up. an alternative is to use an active power-up res et circuit for jtag_trst_n, which drives jtag_trst_n low only at power-up and then holds jtag_trst_n high afterwards with a pull-up resistor. figure 21 shows the electrical connection of the ejtag probe target system connector. figure 21 target system electrical ejtag connection using the ejtag probe in figure 21, the pull-up resistors for jtag_tdo and rst*, the pu ll-down resistor for jtag_trst_n, and the series resistor for jtag_tdo must be adjusted to the specific design. however, the recommended pull-up/down resistor is 1.0 k because a low value reduces crosstalk on the cable to the connector, allowing higher jtag_tck frequencies. a typical value for the series resistor is 33 . recommended resistor values have 5% toler- ance. if a probe is used, the pull-up resistor on jtag_tdo must ensure that the jtag_tdo level is high when no probe is connected and the jtag_tdo output is tri-stated. this requirement allows reliabl e connection of the probe if it is hooked-up when the power is al ready on (hot plug). the pull-up resistor value of around 47 k should be sufficient. optional diodes to protect against overshoot and undershoot voltage can be added on the signals of the chip with ejtag. if a probe is used, the rst* signal must have a pull-up resistor bec ause it is controlled by an open-collector (oc) driver in t he probe, and thus is actively pulled low only. the pull-up resistor is responsible for the high value when not driven by the probe of 25pf. the inpu t on the target system reset circuit must be able to accept the rise time when the pu ll-up resistor charges the capacitance to a high logical level. v cc i/o must connect to a voltage reference that drops rapidly to below 0.5v when the ta rget system loses power, even with a capacitive load of 25pf. the probe can thus detect the lost power condition. for additional information on ejtag, refer to chapter 23 of the rc32365 user reference manual. gnd 1 gnd gnd gnd gnd trst* tdi tdo tms tck rst* jtag_trst_n jtag_tdi jtag_tdo ejtag_tms jtag_tck gnd vdd gnd pull-up pull-down series-res. coldrstn target system reset circuit pull-up other reset sources rc32365 no connect or rstn vsense 2 gnd gnd gnd gnd gnd gnd gnd no connect no connect no connect gnd pull-up vcc i/o voltage reference 23 24
33 of 44 october 5, 2005 rc32365 voltage sense signal timing figure 22 voltage sense signal timing the target system must ensure that t rise is obeyed after the system reaches 0.5v (t active ), so the probe can use this value to determine when the target has powered-up. the probe is allowed to measure the t rise time from a higher value than t active (but lower than vcc i/o minimum) because the stable indication in this case comes later than the time when ta rget power is guaranteed to be stable. if jtag_trst_n is assert ed by a pulse at power-up, this reset must be completed after t rise . if jtag_trst_n is asserted by a pull-down resistor, the probe will control jtag_trst_n. at power-down, no power is indicated to the probe when vcc i/o drops under the t active value, which the probe uses to stop driving the input signals, except for the probe rst*. ac test conditions figure 23 output loading for ac timing phase-locked loop (pll) the processor aligns the pipeline clock, pclock, to the master input clock (clk) by using an internal phase-locked loop (pll) c ircuit that generates aligned clocks. inherently, pll circuits are only capable of gener ating aligned clocks for master input clock (clk) frequencies within a limited range. pll analog filter the storage capacitor required for the phase-locked loop circuit is contained in the rc32365. however, it is recommended that t he system designer provide a filter network of passive components for the pll power supply. v cc pll (circuit power) and v ss pll (circuit ground) should be isolated from v cc core (core power) and v ss (common ground) with a filter circuit such as the one shown in figure 24. vsense t rise_16f t active 1.5v parameter value units input pulse levels 0 to 3.0 v input rise/fall 3.5 ns input reference level 1.5 v output reference levels 1.5 v ac test load 35 pf rc32365 output . 50 50 test point
34 of 44 october 5, 2005 rc32365 because the optimum values for the filter components depend upon the application and the system noise environment, these values should be considered as starting points for further experim entation within your specific application. figure 24 pll filter circuit for noisy environments recommended operating supply voltages recommended operating temperatures capacitive load deration refer to the rc32365 ibis model which can be found at the idt web site (www.idt.com). power-on rampup the 2.5v v cc core and v cc pll supplies can be fully powered without the 3.3v v cc i/o supply. however, the v cc i/o supply cannot exceed the v cc core and v cc pll supplies by more than 1 volt during power up. a sustained large power difference could potentially damage the part. inputs should not be driven until the part is fully powered. specifically, the input high voltages should not be applied until the v cc i/o supply is powered. there is no special requirement for how fast v cc i/o ramps up to 3.3v. however, all timing references are based on a stable v cc i/o. symbol parameter minimum typical maximum unit v ss common ground 0 0 0 v v ss pll pll ground v cc i/o i/o supply 3.135 3.3 3.465 v cc core internal logic supply 2.375 2.5 2.625 v cc pll pll supply table 14 rc32365 operating supply voltages grade temperature commercial 0 c+ 70 c ambient industrial -40 c+ 85 c ambient table 15 rc32365 operating temperature 10 f 0.1 f 100 pf vcc vss vccpll vsspll 10 ohm 1 1. this resistor may be required in noisy circuit environments. rc32365
35 of 44 october 5, 2005 rc32365 dc electrical characteristics the values given below are based on systems running at recommended supply voltages, as shown in table 14. note: for a complete list of i/o types, see table 2. power consumption parameter min max unit conditions low drive output with schmitt trigger input (sti) i ol ?7.3mav ol = 0.4v i oh ?-8.0mav oh = (v cc i/o - 0.4) v il ?0.8v ? v ih 2.0 (v cc i/o + 0.5) v ? high drive output with standard input i ol ?9.4mav ol = 0.4v i oh ?-15mav oh = (v cc i/o - 0.4) v il ?0.8v ? v ih 2.0 (v cc i/o + 0.5) v ? clock drive output i ol 39 ? ma v ol = 0.4v i oh -24 ? ma v oh = (v cc i/o - 0.4) pci i oh (ac) switching -12(v cc i/o) ? ma 0 < v out < 0.3(v cc i/o) -17.1(v cc i/o - v out )? ma0.3(v cc i/o) < v out < 0.9(v cc i/o) ? -32(v cc i/o) ma 0.7(v cc i/o) i ol (ac) switching +16(v cc i/o) ma v cc i/o > v out > 0.6(v cc i/o) +26.7(v out ) ma 0.6(v cc i/o) > v out > 0.1(v cc i/o) ? +38(v cc i/o) ma v out = 0.18(v cc i/o) v il -0.3 0.3(v cc i/o) v ? v ih 0.5(v cc i/o) 5.5 v ? capacitance c in ?10pf ? leakage i/o leak ?20 a? table 16 dc electrical characteristics parameter 150mhz unit conditions typical max. icci/o 60 80 ma c l = 25pf (affects i/o) t a = 25 o c maximum values use the maximum voltages listed in table 14. typical values use the typical voltages listed in table 14. i cc core normal mode 710 750 ma standby mode 1 1. riscore 32300 cpu core enters standby mode by executing wait instructions; however, other logic continues to function. standby mode reduces power consumption by 0.6 ma per mhz of the cpu pipeline clock, pclk. 620 660 ma power dissipation normal mode 2.07 2.2 w standby mode 1 1.8 2.0 w table 17 rc32365 power consumption
36 of 44 october 5, 2005 rc32365 power curve the following graph contains a power curve that s hows power consumption at various bus frequencies. figure 25 typical power usage absolute maximum ratings symbol parameter min 1 1. functional and tested operating conditions are given in table 14. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliabil- ity or cause permanent damage to the device. max 1 unit v cc i/o i/o supply voltage -0.6 4.0 v v cc core core supply voltage -0.3 3.0 v v cc pll pll supply voltage -0.3 3.0 v vimin input voltage - undershoot -0.6 ? v vi i/o input voltage gnd v cc i/o+0.6 v ta, industrial ambient operating temperature -40 +85 c ta, commercial ambient operating temperature 0+70 c tstg storage temperature -40 +125 c table 18 absolute maximum ratings typical power curve 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 70 75 80 85 90 95 100 system bus speed (mhz) power (w @ 3.3v io & 2.5v core)
37 of 44 october 5, 2005 rc32365 package pin-out ? 256-pin cabga the following table lists the pin numbers and signal names for the rc32365. pin function alt pin function alt pin function alt pin function alt a1 mii0rxd[0] e1 gpio[15] 1 j1 pcigntn[1] n1 pciad[4] a2 mii0rxdv e2 jtag_trst_n j2 pcidevseln n2 pciad[20] a3 mii0rxer e3 jtag_tdo j3 pcigntn[0] n3 pciad[19] a4 mii0txclk e4 jtag_tdi j4 pciframen n4 pciad[11] a5 mii0txd[2] e5 v cc core j5 v cc i/o n5 pciad[13] a6 mii0crs e6 v cc i/o j6 v ss n6 pciad[15] a7 vsspll e7 v cc i/o j7 v ss n7 boen[0] a8 mii1rxclk e8 v cc i/o j8 v ss n8 csn[2] a9 mii1txd[2] e9 v cc i/o j9 v ss n9 csn[3] a10 mii1cl e10 v cc i/o j10 v ss n10 rwn a11 jtag_tck e11 v cc i/o j11 v ss n11 mdata[1] a12 gpio[9] 1 e12 v cc core j12 v cc i/o n12 mdata[3] a13 gpio[5] 1 e13 maddr[5] j13 sdwen n13 mdata[12] a14 gpio[3] 1 e14 maddr[16] j14 sdclkinp n14 mdata[30] a15 gpio[1] 1 e15 maddr[17] j15 bwen[2] n15 mdata[11] a16 maddr[10] e16 maddr[6] j16 bwen[3] n16 mdata[27] b1 mii0rxd[3] f1 gpio[14] 1 k1 pcicben[1] p1 pciad[5] b2 mii0rxd[1] f2 gpio[13] 1 k2 pcicben[2] p2 pciad[21] b3 mii0rxclk f3 pcitrdyn k3 pcicben[0] p3 pciad[23] b4 mii0txer f4 pcistopn k4 pciclk p4 pciad[10] b5 mii0txd[3] f5 v cc core k5 v cc i/o p5 pciad[28] b6 mii0cl f6 v cc i/o k6 v ss p6 pciad[30] b7 vccpll f7 v ss k7 v ss p7 bdirn b8 mii1rxdv f8 v ss k8 v ss p8 csn[1] b9 mii1txd[3] f9 v ss k9 v ss p9 csn[4] b10 mii1crs f10 v ss k10 v ss p10 waitackn b11 gpio[12] 1 f11 v cc i/o k11 v ss p11 mdata[17] b12 gpio[8] 1 f12 v cc core k12 v cc core p12 mdata[19] b13 gpio[4] 1 f13 maddr[3] k13 bwen[1] p13 mdata[5] b14 gpio[2] 1 f14 maddr[14] k14 rasn p14 mdata[9] b15 maddr[21] f15 maddr[15] k15 casn p15 mdata[10] b16 maddr[20] f16 maddr[4] k16 bwen[0] p16 mdata[26] c1 miimdc g1 pcirstn l1 pciad[16] r1 pciad[6] c2 miimdio g2 pciserrn l2 pciad[1] r2 pciad[7] table 19: 256-pin cabga package pin-out (part 1 of 2)
38 of 44 october 5, 2005 rc32365 c3 mii0rxd[2] g3 pciperrn l3 pciad[0] r3 pciad[24] c4 mii0txenp g4 pcireqn[0] l4 pcicben[3] r4 pciad[25] c5 mii0txd[1] g5 v cc core l5 v cc core r5 pciad[27] c6 mii1rxd[3] g6 v ss l6 v cc i/o r6 pciad[29] c7 mii1rxd[0] g7 v ss l7 v ss r7 pciad[31] c8 mii1rxer g8 v ss l8 v ss r8 boen[1] c9 mii1txenp g9 v ss l9 v ss r9 oen c10 mii1txd[0] g10 v ss l10 v ss r10 mdata[16] c11 ejtag_tms g11 v ss l11 v cc i/o r11 mdata[18] c12 gpio[10] 1 g12 v cc i/o l12 v cc core r12 mdata[20] c13 gpio[6] 1 g13 maddr[1] l13 clk r13 mdata[21] c14 gpio[0] 1 g14 maddr[12] l14 sdclkout r14 mdata[7] c15 maddr[9] g15 maddr[13] l15 mdata[15] r15 mdata[24] c16 maddr[19] g16 maddr[2] l16 mdata[31] r16 mdata[25] d1 sdi h1 pcipar m1 pciad[18] t1 pciad[22] d2 coldrstn h2 pcireqn[1] m2 pciad[3] t2 pciad[8] d3 sdo h3 pcilockn m3 pciad[2] t3 pciad[9] d4 sck h4 pcirdyn m4 pciad[17] t4 pciad[26] d5 mii0txd[0] h5 v cc i/o m5 v cc core t5 pciad[12] d6 mii1rxd[2] h6 v ss m6 v cc i/o t6 pciad[14] d7 mii1rxd[1] h7 v ss m7 v cc i/o t7 rstn d8 mii1txer h8 v ss m8 v cc i/o t8 csn[0] d9 mii1txclk h9 v ss m9 v cc i/o t9 csn[5] d10 mii1txd[1] h10 v ss m10 v cc i/o t10 mdata[0] d11 jtag_tms h11 v ss m11 v cc i/o t11 mdata[2] d12 gpio[11] 1 h12 v cc i/o m12 v cc core t12 mdata[4] d13 gpio[7] 1 h13 sdcsn[0] m13 mdata[14] t13 mdata[6] d14 maddr[7] h14 sdcsn[1] m14 mdata[13] t14 mdata[22] d15 maddr[18] h15 maddr[11] m15 mdata[28] t15 mdata[23] d16 maddr[8] h16 maddr[0] m16 mdata[29] t16 mdata[8] pin function alt pin function alt pin function alt pin function alt table 19: 256-pin cabga package pin-out (part 2 of 2)
39 of 44 october 5, 2005 rc32365 rc32365 power pins rc32365 ground pins v cc i/o v cc i/o v cc core v cc pll e6 j5 e5 b7 e7 j12 e12 e8 k5 f5 e9 l6 f12 e10 l11 g5 e11 m6 k12 f6 m7 l5 f11 m8 l12 g12 m9 m5 h5 m10 m12 h12 m11 table 20 rc32365 power pins v ss v ss v ss v ss pll f7 h7 k6 a7 f8 h8 k7 f9 h9 k8 f10 h10 k9 g6 h11 k10 g7 j6 k11 g8 j7 l7 g9 j8 l8 g10 j9 l9 g11 j10 l10 h6 j11 table 21 rc32365 ground pins
40 of 44 october 5, 2005 rc32365 alternate pin functions pin primary alt #1 c14 gpio[0] u0sout a15 gpio[1] u0sinp b14 gpio[2] maddr[22] a14 gpio[3] maddr[23] b13 gpio[4] maddr[24] a13 gpio[5] maddr[25] c13 gpio[6] n/a d13 gpio[7] sdckenp b12 gpio[8] cen1 a12 gpio[9] cen2 c12 gpio[10] regn d12 gpio[11] iordn b11 gpio[12] iowrn f2 gpio[13] pcireqn[2] f1 gpio[14] pcigntn[2] e1 gpio[15] pcimunitn table 22 alternate pin functions
41 of 44 october 5, 2005 rc32365 rc32365 pinout ? top view 1 23 4 5 67 8 9 10 11 12 13 14 15 16 v ss (ground) v cc i/o (power) a b v cc core (power) c d e f g h j k l m n p r t vsspll vccpll
42 of 44 october 5, 2005 rc32365 package drawing - 256-pin cabga
43 of 44 october 5, 2005 rc32365 package drawing - page two
44 of 44 october 5, 2005 rc32365 corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: rischelp@idt.com phone: 408-284-8208 ordering information valid combinations 79rc32t365 - 150bc 256-pin cabga package, commercial temperature 79rc32t365 - 150bcg 256-pin cabga package, commercial temperature (green) 79rc32t365 - 150bci 256-pin cabga package, industrial temperature 79rc32t365 - 150bcgi 256-pin cabga package, industrial temperature (green) 79rcxx yy xxxx 999 a a operating voltage device type speed package temp range/ process t 150 blank commercial temperature (0c to +70c ambient) 150 mhz pipeline clk 2.5v +/-5% core voltage integrated core processor product type 79rc32 32-bit embedded microprocessor 256-pin cabga bc 365 i industrial temperature (-40 c to +85 c ambient) 256-pin green cabga bcg

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